Big Data applications, like Machine Learning and Artificial Intelligence, require access to a large dataset to train the algorithm or neural network. This creates a need to move all the data required by the application to the processor. Moving large amounts of data over a network takes time, money, and ties up network bandwidth. This is not a sustainable or optimum approach.

The root cause resides in the current von Neumann computer architecture, followed for over 30 years. In this model, the rest of the computer system revolves around the processor (termed a “general computing architecture.”). One proposed solution is to make the memory the focal point of the computer architecture–memory-centric computer architecture. However, implementation is complex since all current operating systems and applications are built around the von Neumann computer. Multiple processors, using a large pool of memory, need to implement cache coherency to avoid two processors attempting to access or rewrite a memory location that might be needed by another processor. The move to highly-parallel processing has made some inroads into multiple cores accessing memory cache and coherency, however they have used a relatively small memory space. Expanding the shared memory to multiple TB’s of data adds more complexity to the shift in architecture. Our investigations are directed at understanding what it will take to transition to a memory-centric architecture.

Two different memory technologies are currently used as the memory that is accessed by the CPU, SRAM and DRAM. Both are volatile, meaning data stored will be lost when the power fails or is turned off. A new class of memory (Persistent or Storage Class Memory, SCM) is being developed that is non-volatile i.e. data does not disappear when power is lost

Memory located close to the CPU needs fast access time, or latency close to the CPU clock speed, for it to be used as CPU cache memory. The latency of both SSD and HDD data storage devices is too slow to be used. Differentiating memory from storage is key when discussing this topic (here, memory refers to bit-addressable memory utilized for registers and cache accessed by the CPU, while storage refers to devices using systems to organize and store data, and is not bit-addressable).

Some designs of non-volatile memory with low latency can compete with DRAM: these are called MRAM (Magnetoresistive Random Access Memory) or STT-MRAM (Spin Transfer Torque Magnetoresistive Random Access Memory). Other technologies that are between DRAM and SSD in latency are PCM (Phase Change Memory) or ReRAM (Resistive Random Access Memory). Western Digital has researched non-volatile memory for several years, ranging from basic materials research (including cell physics and design), to memory cell array fabrication and testing. All these efforts will be combined when a product is launched into this emerging market. These three areas are the “hardware” side of this technology. Other research targets the “software” implications of the transition to non-volatile memory.

Software programmers have been writing software for years using volatile DRAM and SRAM, consequently there are many provisions in the code to deal with this fact. What will happen if DRAM is replaced with persistent nonvolatile memory? Additionally if memory is added to the computer or server that is close to DRAM in latency, how would this new SCM (Storage Class Memory) be used? What changes would need to be made to the kernel and operating system? How does this impact the SaaS (Storage as a Service) segment of the industry? How does this impact the disaster recovery segment? In reality every segment of the software hierarchy will need to review how this change would impact their products and services. Changes do not happen overnight, so there will be a period of time during the transformation to non-volatile memory where the path is not clear, backward compatibility must be considered. Alternatively companies may choose to offer products based on the new memory configuration of the computer system to quickly take advantage of the non-volatile memory. Will adoption of the change impact cloud providers first, or will enterprise data centers lead the way?

With the number of unknowns associated with this transformation how does one go about it? If you step back and think about persistent memory it has the potential to be one of the most disruptive technologies introduced to the industry, and it has the potential to impact our daily interaction with our devices. Changing an entire industry will take time, working with standardization groups, working with the open source community, working with companies with closed code.

Western Digital’s memory-centric activities requires an understanding of the use cases that would benefit from a memory-centric architecture, the use case we have chosen is Machine Learning (ML). Machine Learning and Artificial Intelligence are fast becoming part of our everyday life, and looking forward it will continue to develop and play a role in many aspects of our life. Western Digital does have engineering projects investigating the use of ML & AI in our products and processes, however the efforts in the CTO Office are directed at ML & AI needs in the future. Two main areas of investigations driven by the CTO Office are accelerators and algorithms, both of which are continuing to evolve.

Specially designed accelerators are particularly useful for ML & AI applications. An accelerator is designed for a specific application where the microarchitecture and instruction set are limited to only what is needed for ML applications. Because of this accelerators are function specific and greatly reduce the time it takes to process a large data set. Accelerators are an example of a how specialized chips are augmenting the traditional general computing CPU’s to reduce both time and energy requirements for ML applications. Studies have shown a potential of ~10x or more improvement in energy and processing speed when comparing standard CPU designs to optimized designs for a specific workload. Applications using ML & AI are skyrocketing currently, creating opportunities for accelerators designed specifically for these data intensive applications.

Why is Western Digital, historically a data storage company, launching this initiative and investing in
RISC-V?

There's a couple reasons. To start, the open source model, proven by the success of Linux, now has a hardware platform in the RISC-V Foundation to unleash the next generation of innovation. Another reason is the configurability RISC-V provides is unparalleled.  By leveraging the open collaboration and flexibility of RISC-V, Western Digital can create processors that are purpose-built for data centric applications.  Nearly every Western Digital product has some kind of processing core included. We currently use one billion cores every year in our products, and are publicly committed to transition our processor cores to RISC-V. While working to incorporate RISC-V cores into our products, we are also working to develop the supporting ecosystem, where data is the key asset to drive the next generation of innovation.